The present invention relates to integrated circuits structures and fabrication methods, and chemical mechanical polish (CMP) stops used for dielectric planarization over metallization.
Background: Chemical Mechanical Polishing
Chemical mechanical polishing (CMP) is a planarization technique which has become increasingly important in integrated circuit processing in the 1990s. CMP, unlike most other planarization techniques, provides global planarization. This global planarization avoids problems of step coverage, and hence helps achieve the numerous multiple layers of metallization which are now desired. Global planarization also improves lithographic resolution, by removing constraints on the depth of field.
However, optimum uniformity of CMP processes has not yet been achieved due to the relationship between polish rates and features sizes. To correct these problems, several schemes have been attempted, including the use of polish stop layers. These polish stop layers provide a flat, polish-resistant surface to be an endpoint in the planarization.
Background: Interlevel Dielectric over Metals
It is desirable to planarize the interlevel dielectric (ILD) used over metallization layers. Non-uniformity of the ILD is contributed to by the non-uniformity of underlying layers, variations in the ILD deposition process, and non-uniformity of planarization due to variations in pattern density. This lack of uniformity limits the minimum thickness of oxide which must be left over metal layers after CMP, but also causes variations in via resistances due to the variations in via depth through the oxide.
Background: Silicon Nitride as CMP Stop
Current state of the art uses silicon nitride as both a silicon etch hardmask and as a CMP stop layer for chemical-mechanical polishing (CMP). Since the removal selectivity of silicon dioxide to silicon nitride is only 4:1 or 5:1 using industry-accepted slurries, the silicon nitride layer is not an effective CMP polish stop layer. Non-uniformity due to polish and pattern effects can cause the dielectric SiO2 and Si3N4 over small isolated active device features to be polished much more quickly than other features, thus causing damage to these small active regions.
Some attempts have been made to achieve higher oxide:nitride selectivities by using other chemistries, but these attempts have required additional steps to be performed or required more expensive materials, so that more cost effective alternatives are sought.
Background: Silicon Carbide as CMP Stop
Applications commonly owned by the assignee of this application (attorney docket TI-26419P, 60/068,661, filed Dec. 23, 1997 and attorney docket TI-26419P1, provisional No. 60/086,215, filed May 21, 1998), both of which are hereby incorporated by reference, disclose the use of silicon carbide as an etch stop in the formation of such isolation features as trench isolation. In this application, standard polishing chemistries can very easily give an extremely high selectivity (50:1 or better) between silicon dioxide and silicon carbide.
Planarization Over Metal Lines
The present application discloses a method for planarizing the interlevel dielectric (ILD) material over metallization lines using silicon carbide layers as the stop layer in chemical mechanical polishing, or alternatively, using a silicon carbonitride or silicon carboxide.
Advantages of the disclosed methods and structures, in various embodiments, can include increased uniformity of the via resistances since the variation in oxide thicknesses over metal leads is reduced;